View PMB2349_38305.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Wireless Components
Optimized RF/IF Dual PLL Frequency Synthesizer PMB 2349 Version 1.0
Specification May 2000
Confidential TARGET SPECIFICATION
CONFIDENTIAL Revision History: Current Version: May 2000 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG.
Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG i. Gr. 10.05.00. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PMB 2349
TARGET SPECIFICATION
Confidential
Product Info
Product Info
General Description Package The PMB 2349 is a RF/IF Dual-PLL frequency synthesizer implemented in Infineon's high speed BiCMOS technology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are P-VQFN-24-3 single- and dual-band digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems. Operation range 2.7 to 5.0 V Ultra low phase noise Ultra low spurious Faster lock-in times New bipolar power modes Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 Fast phase detectors and charge pump outputs without dead zone Switchable polarity and programmable phase detector currents Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing with low voltage baseband circuits Two data registers in PLL2 for fast IF band switching A programmable output port for lock detect or general porpose (VCO switch etc.).
Programmable power down modes High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz PLL2 (IF): 600 MHz Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9
Ordering Information
Type PMB 2349 Ordering Code Package P-VQFN-24
Wireless Components
Product Info
Low operating current consumption
External or internal reference current setting for PD outputs

Features
New programmable Reference Amplifier
Specification, May 2000
1
2.1 2.2 2.3 3.1 3.2 3.3 3.4
Table of Contents
2-1 2-2 2-2 2-3 3-1 3-2 3-3 3-7 3-8 3-8 3-8 3-10 3-10 3-10 3-11 3-11 4-1 4-2 5-1 5-2 5-2 5-3 5-3 5-4 5-6 5-7 5-12 5-12 5-12 5-13 5-14 5-14 5-15 5-15
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Standby Condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Prescaler Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Phase Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Typical Supply Current ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Typical RF Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Typical IF Sensitivity: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Typical Ri Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Charge Pump Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1 Carge Pump Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Typical Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PMB 2349
preliminary
Confidential
Product Description
2.1 Overview
The PMB 2349 is a RF/IF Dual-PLL frequency synthesizer implemented in Infineon's high speed BiCMOS technology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are single- and dualband digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems.
2.2 Features
Operation range 2.7 to 5.0 V Ultra low phase noise Ultra low spurious Faster lock-in times New bipolar power modes New programmable Reference Amplifier External or internal reference current setting for PD outputs Low operating current consumption Programmable power down modes High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz, PLL2 (IF): 600 MHz Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9 Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 Fast phase detectors and charge pump outputs without dead zone Switchable polarity and programmable phase detector currents Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing with low voltage baseband circuits Two data registers in PLL2 for fast IF band switching A programmable output port for lock detect or general porpose (VCO switch etc.).
Wireless Components

2-2
Specification, May 2000
PMB 2349
preliminary
Confidential
Product Description
2.3 Package Outlines
VQFN-24-3.eps
Figure 2-1
P-VQFN-24
Wireless Components
2-3
Specification, May 2000
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Standby Condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Prescaler Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Phase Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
PMB 2349
preliminary
Confidential
Functional Description
3.1 Pin Configuration
GND1
VPD2
CP2
GND2
IFX
16
15
14
20
19
18
BACK
21
17
13 12
NC R e xt 11 M FO 10 CLK 9 BACK DA 8
VCC2
22
PM B 2349
VCC1
23
NC
24 1 2 3 4 5 6 7 EN
CP1
GND1
VPD1
RF1
RFX
GND2
RI
IF
Pin_config.wmf
Figure 3-1
Pin Configuration
Wireless Components
3-2
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 23 1 2 Symbol VCC1 VPD1 CP1
P D O u tp ut E q u iva le n t
Equivalent I/O-Schematic
Function Positive supply voltage for CMOS circuitry Positive supply voltage for charge pump of PLL1 PLL1 charge pump output Phase detector tristate charge pump output
3 *2 p F CP1
E SD
3 4
GND1 RF1
R F a n d IF In p u t E q u iva le n t
Ground for CMOS circuitry RF frequency input 1 RF input with highly sensitive preamplifier for PLL1. AC coupling must be set up.
5 /1 6
5
RFX
R F /IF
6 /1 5 R F x/IF x
RF frequency input (inverted) RF input with highly sensitive preampifier for PLL1. AC coupling must be set up
6
GND2
Ground for bipolar circuitry
Wireless Components
3-3
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. 7 Symbol EN
S e ria l C o n tro l In p ut E q u iva le n t
Equivalent I/O-Schematic
Function 3-Wire bus input: Enable Enable input of the serial control interface with Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data are transferred to the registers with the positive edge of the EN-signal. 3-Wire bus input: Data Data input of the serial control interface with Schmitt-Trigger input stage.The serial data are read into the internal shift register with the positive edge of CLK.
7 5 k 8 CLK *2 p F 560
ESD
8
DA
S e ria l C o n tro l In p ut E q u iva le n t
7 5 k 9 DA *2 p F 560
ESD
10
CLK
S e ria l C o n tro l In p ut E q u iva le n t
7 5 k 10 EN *2 p F 560
3-Wire bus input: Clock Clock input of the serial control interface with Schmitt-Trigger input stage
ESD
11
MFO
L D a s L o ck D e te cto r
11 *2 p F L D /fo
ESD
Lock detector output Unipolar output of the phase detector in the form of a pulse-width modulated signal. In the locked state the output signal is at H-level. In standby mode the output is resistive. For test purpose the push pull output fo is enabled.
Wireless Components
3-4
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. 12 Symbol Rext
O S W O utp u t E q u iva le n t
Equivalent I/O-Schematic
Function CP & Prescaler reference current setting External resistor for CP & Prescaler reference current setting.
12
2pF
R e xt
ESD
14
RI
R I In put E qu ivale nt STDBY
5 00K
13 RI 2 pF ESD
5 60
Reference frequency input Input with highly sensitive preamplifier. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals.
/S T D B Y
15 16
GND2 IFX
R F a n d IF In p u t E q u iva le n t
Ground for bipolar circuitry IF frequency input (inverted) IF input with highly sensitive preampifier for PLL2. AC coupling must be set up.
17
IF
5 /1 6 R F /IF 6 /1 5 R F x/IF x
IF frequency input IF input with highly sensitive preampifier for PLL2. AC coupling must be set up.
18
GND1
Ground for CMOS circuitry
Wireless Components
3-5
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. 19 Symbol CP2
P D O u tp ut E q u iva le n t
Equivalent I/O-Schematic
Function Phase detector tristate charge pump output for PLL2
18 *2 p F CP2
E SD
20 22 9+21 13+24
VPD2 VCC2 BACK NC
Positive supply voltage for charge pump 2. Positive supply voltage for bipolar circuitry Backplane - BIPOLAR ground recommended not connected
Wireless Components
3-6
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
3.3 Functional Block Diagram
PLL1 (RF)
VCC1
Mod1
Modulus Control
VCC2
14 Bit N-Counter VPD1 Data Reg. Shadow Reg. PD1 Phase Detector Shift Register
6 Bit A-Counter VPD2 Data Reg. Shadow Reg. Shift Register Phase Detector PD2
GND1
Mod1
64/65 32/33
14 Bit R1-Counter Data Reg. Shadow Reg. Shift Register
14 Bit R1-Counter
GND1
RF
Data Reg. Shift Register
IF
RFX
Mod2
IFX 16/17 8/9
Modulus Control GND2 14 Bit N-Counter EN Multiplexer Dec Serial Control Logic Data Reg. 1 Data Reg. 2 Multiplexer Data Reg. 1 Data Reg. 2 4 Bit A-Counter RI GND2
DA
Bias Iref
REXT
Shift Register CLK
Shift Register LD fo LD
PLL2 (IF)
Funct_block.wmf
Figure 3-2
Functional Block Diagram
Wireless Components
3-7
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
3.4 Circuit Description
3.4.1
General Description
The PMB 2349 consists of two fully programmable PLLs, one for the RF and one for the IF frequency range. Each PLL contains a high frequency dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with charge pump output. The two synthesizers are controlled via the common serial 3-wire interface. The reference frequency is applied at the common RI-input and divided by the R-counter of each PLL. Its maximum value is 45 MHz. The RF and IF input frequencies will be divided by the corresponding prescalers with a programmable 32/32 or 64/65 (RF) and 8/9 or 16/17 (IF) divide ratio and the following programmable A/N-counters. The maximum RF frequency value is 2.8 GHz and 600 MHz for the IF frequency. The phase and frequency detectors with the charge pumps have a linear operating range without a dead zone for very small phase deviations. The multifunctional output port LD/MFO can be programmed as lock detector and general purpose output.
3.4.2
Programming
Programming of the IC is done via the serial data interface. The content of the bus telegram (serial data format) is assigned to the functional units according to the address. The most significant bit (MSB) of the serial data formats is shifted first. The short control data format allows a fast PD-current change. The long control data format allows the programming of asynchronous or synchronous data acquisition of PLL1 (RF), 4 different PD-output current modes for the PLL1 and 1 PD-output current modes for PLL2, polarity setting of the PDoutput signals, 2 standby modes, charge pump pulse width and the prescaler divide ratio. The A/N-counter data format of PLL1 contains the A/N-counter value.. The data format of PLL2 comprise the counter values as well. The R-counter data format contains the R-counter values. The PLL1 (RF) of PMB 2349 offers the possibility of synchronous counter and charge pump current programming to avoid phase errors at the phase detector when R- and A-/N-counter are programmed one after another or the charge pump current is altered.
Wireless Components
3-8
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
Asynchronous Mode: The serial data is written directly to the data registers of the addressed counter with the Enable pulse. As each counter is loading the new starting value after it is decremented to zero", the counters changes therefore their counter values asynchronously to the others. Synchronous Mode (only for RF): In this mode counter programming is controlled by the R- and N-counters. The serial data (exception: higher part of long control data format) is first written with the Enable pulse to the corresponding shadow registers. From there the values for R-counter, A-/N-counter and charge pump current values of short/long control data format are loaded into the corresponding data register when the Ncounter reaches zero+1". Therefore the change of all counter states is synchronised to the reloading of the N-counter to avoid additional phase error caused by the programming. The transfer of the charge pump current values into the corresponding data register is tied to the N-counter loading, but follows the loading of the N-data register in the distance of one N-counter dividing ratio. This guarantees that a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous programming sequence: 1. Setting of synchronous counter programming by bit c13 of long control data format. 2. Programming of the R-counter, and optional short control data format. With the Enable signal data is loaded into the shadow registers. 3. Programming of the A/N-counter. Data is loaded into shadow registers, the EN-signal starts the synchronous transfer to the data registers.
Synchronous data programming is of especial advantage, when large frequency steps are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid - "rough" - transient response. This method increases the fundamental frequency by nearly the square root of the reference frequency ratio and therefore the settling time is reduced. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A "fine" lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN (DCS 1800) and PCS systems the synchronous mode should be used to achieve best performance of the PMB 2347.
Wireless Components
3-9
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
3.4.3
Standby Condition (power down)
Each PLL of the PMB 2349 has two programmable standby modes to reduce the current consumption (standby 1, standby 2). Standby 1: The corresponding PLL is switched off, the current consumption is reduced below 1 A. Standby 2: The corresponding counters, the charge pump and the outputs are switched off. Only the preamplifier of RI-input stays active. (See standby table)
3.4.4
Divide ratio programming
The frequency of an external VCO controlled by the PMB 2347 is given below:
f RI M f VCO = [ ( P N ) + A ] ------ = ---- f RI R R
with A N . fVCO: fRI: N: A: P: R: M=P*N+A: Note: frequency of the external VCO reference frequency divide ratio of the N-counter divide ratio of the A-swallow counter divide ratio of the prescaler divide ratio of the R-counter total divide ratio for continous frequency steps following condition is necessary
[P N + A] P (P - 1)
3.4.5
Prescaler Divide Ratio
For the highest input frequencies of the prescalers the larger divide ratio is necessary: RF-PLL: 64/65 for frequencies greater 1500 MHz IF-PLL: 16/17 for frequencies greater 375 MHz
Wireless Components
3 - 10
Specification, May 2000
PMB 2349
preliminary
Confidential
Functional Description
3.4.6
Fast wake-up programming
When the circuit is connected to the supply voltage all registers are undefined. Due to the fact that each counter is loading its new start value after it is decremented to zero", the start-up time of the counters with the programmed values is too long for some applications. If the counters are programmed in standby mode 2 and the PLLs are switched afterwards in operating mode, the counters are starting immediatly with the programmed values. Therefore following data transfer sequence is recommended:
Table 3-2 Fast Wake Up Data Transfer Sequence Step 1 2 3 4 Serial Data Transfer Sequence Long Control Word: Asynchronous Mode, Standby2 R-Counter A-/N-Counter Long Control Word: Synchronous Mode, Operating Mode
3.4.7
Phase Detector Outputs
RI fR (RI:R)
RF1/2 fV (RF1:M) (RF2:M)
CP
P-Channel Tri-State N-Channel
positive Polarity CP
P-Channel Tri-State N-Channel
negative Polarity LD
Frequency fV < fR fV lagging
Frequency fV > fR fV leading
Frequency fV = fR lock state
The timing diagram is valid for PLL1 and PLL2.
Wireless Components
3 - 11
Specification, May 2000
4
Applications
Contents of this Chapter
4.1
Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
PMB 2349
preliminary
Confidential
Applications
4.1 Hint
More Information about "Application" see in separate Document APPLICATION NOTE PMB 2349.
Wireless Components
4-2
Specification, May 2000
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 5.5 5.6 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Input Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Charge Pump Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . 5-15
PMB 2349
preliminary
Confidential
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings # Parameter Symbol Limit Values min 1 2 3 4 5 6 7 8 Supply Voltage Input Voltage Output Voltage Total power dissipation Ambient temperature Storage temperature Thermal Resistance ESD Integrity (according to MIL 883 Method 3015.7) except Pins Vpd1[2] and Vpd2[19] VCC1/2 VI VO Ptot TA TStg RthJA VESD -40 -50 -0.3 -0.3 GND max 5.5 VCC1/ 2+0.3 VCC1/2 300 85 125 170 0.5 V V V mW C C K/W KV preliminary in operation Unit Remarks
Wireless Components
5-2
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed.
Table 5-2 Operating Range, VCC1/2= 2.7V - 5.0V, TAMB=-27C # Parameter Symbol Limit Values min 1 2 3 4 5 6 7 8 Supply Voltage Input frequency RF Input frequency IF Input reference frequency CP-output current of PLL1 CP-output current of PLL2 CP-output voltages Ambient temperature VCC1/2 RF IF Ri / ICP1 / / ICP2 / VCP1/2 TA 0.5 -40 2.7 250 100 1 max 5.0 2800 600 45 4 +20% 1 +20% VPD1/2 - 0.5 85 V MHz MHz MHz mA mA V C VCC1/2 = 3.6V Unit Test Conditions L Item
This value is guaranteed by design.
Wireless Components
# 1 2 3 4 5 6 7
5.1.3
Typical Supply Current ICC
Table 5-3 Typical Supply Current ICC Parameter Symbol min Supply Voltage Supply current: PLL1 & PLL2 active PLL1 active, PLL2 standby PLL1 standby2, PLL2 active PLL1 & PLL2 standby 2 PLL1 & PLL2 standby 1 ICC1/2 ICC1/2 ICC1/2 ICC1/2 ICC1/2
-20% -20% -20%
Limit Values typ 2.7 max
Unit
Test Conditions
Item
VCC1/2
V
9402 7840 3065 120 <1
+20% +20% +20%
A A A A A Note 1)
1) VCC1/2= 2.7V, REXT = 12k, RF-/ IF- and Ri-inputs are open, 3WB optical interface, ICP1 = 4.0mA, ICP2 = 2.0mA, Iref = 100 A
5-3
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.1.4
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB= 27C Symbol min Limit Values typ max Unit Test Conditions D Item
Input Signals DA, CLK, EN (Schmitt-Trigger input stage) H-input voltage L-input voltage Input capacity H-input current L-input current Input Signal RI Input voltage Slew rate Input capacity H-input current L-input current Input Signals RF Input voltage Input voltage Input voltage Input voltage Input Signals IF Input voltage Input voltage Input voltage PI PI PI -15 -25 -25 +4 -5 -15 dBm dBm dBm f = 50 - 300 MHz f = 200 - 450 MHz f = 450 - 600 MHz 4.1 4.2 4.3 PI PI PI PI -10 -10 -20 -15 0 0 -10 -10 dBm dBm dBm dBm f = 150-500 MHz f = 500-1500 MHz f = 1500-2500 MHz f = 2500-2800 MHz 3.1 3.2 3.3 3.4 CI IH VI -30 VI 100 4 3 30 mVrms V/s pF A A VI=VCC1=3.6V VI=GND 2.13 f= 4 - 45 MHz, VCC1=3.6V VCC1=2.7 - 5.0 V 2.10 VIH VIL CI IH IL -10
0.7 VCC
VCC
0.3 VCC
V V pF A A VI=VCC2=3.6V VI=GND 2.3 2.4
5 10
Wireless Components
5-4
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB= 27C (continued) Symbol Output Current ICP1 Limit Values Unit Test Conditions D Item
"2.0 mA" "2.8 mA" "4.0 mA" "Tristate" Output Current ICP2
ICP1 ICP1 ICP1 /ICP1/
-20% -20% -20%
2.0 2.8 4.0 0.1
+20% +20% +20% 10*)
mA mA mA nA
Output Current Offset CP1 & CP2 CP Supply Voltage CP Current Offsett Current Mismatch "1.2 mA" "2.0 mA" "2.8 mA" "4.0 mA" Output Rext VRext IRext VRext IRext 1.2 100 V A
VCC2 = 3.6V, Rext=12k VCC2 = 3.6V, Rext=12k
VPD1/2 ICP-OFF
2.7 -4
3.6 0
5.0 +13
V %
VCP1/2 = VPD1/2/2
ICPMM ICPMM ICPMM ICPMM
% % % %
VPD1=3.6V, VCP1 = VPD1/2 IREF=100 A
Output Signal BSW at BSW/LD-Pin (n-channel open drain) L-output voltage VOL tF 3 0.4 V VCC1 = 2.7 - 3.6V, IOL = 0.3 mA VCC1 = 3.6V, CI = 10pF
Fall time
10
ns
these values are guaranteed by design see chapter 5.5.2 (Charge Pump Performance - Typical Performance) for VCP-range CONSERVATIVE
Wireless Components
5-5
Specification, May 2000
"Tristate"
/ICP2/
0.1
10*)
nA
"1.0 mA"
ICP2
-20%
+20%
mA
VPD1=3.6V, VCP2=VPD2/2 IREF=100A

"1.2 mA"
ICP1
-20%
1.2
+20%
mA
VPD1=3.6V, VCP1=VPD1/2 IREF=100A
5.1 5.2 5.3 5.4 5.5
10.1

PMB 2349
preliminary
Confidential
Reference
5.2 Serial Control Data Format Timing
tWHCL VIH CLK VIL tWLCL
tR
tF
tDS
VIH
DA
VIL
tCLE
tECL
VIH
EN
VIL
tWHEN VIH PORT
VIL
tDEP
Table 5-5 Parameter Symbol Limit Values min. Clock frequency H-pulsewidth (CLK) max. 15 30 MHz ns Unit
CL
tWHCL tWLCL tDS tCLE tECL tWHEN
tR, tR
L-pulsewidth (CLK) Data setup Setup time Clock-Enable Setup time Enable-Clock H-pulsewidth (Enable) Rise, fall time Propagation delay time EN-PORT
30 20 20 20 60 10 1
ns ns ns ns ns s s
tDEP
Wireless Components
5-6
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.3 Serial Control Data Formats
Table 5-6 Address of Data Formats Address a2
0 0 1 1 0 0 1 1
Data Format a0
0 0 0 0 1 1 1 1 Short Control Data Format Long Control Data Format A-/N-Counter R-Counter Short Control Data Format Long Control Data Format A-/N-Counter R-Counter
Addressed PLL
a1
0 1 0 1 0 1 0 1
PLL1 (RF) PLL1 (RF) PLL1 (RF) PLL1 (RF) PLL2 (IF) PLL2 (IF) PLL2 (IF) PLL2 (IF)
In general each PLL can independently be addressed without affecting the other PLL (See also Test Modes).
NOTE: MSB of all serial data is shifted first
Table 5-7 Short Control Data Formats PLL 1 Bit
LSB 0 1 2 3 4 5 6 MSB 0 0 0
PLL 2 Function
Address Address Address LD InActive CP current 2 CP current 1 PLLSel
Bit
a0 a1 a2 c0 c1 c2 c3
Bit
LSB 0 1 2 3 4 5 6 MSB 1 0 0
Bit
a0 a1 a2 c0 c1 c2 c3
Function
Address Address Address reserved reserved CP current reserved
Table 5-8 Long Control Data Formats PLL 1 Bit
LSB 0 1 2 3 4 5 6 7 0 1 0
PLL 2 Function
Address Address Address LD inactive CP current 2 CP current 1 PLLSel PSC Div. Ratio
Bit
a0 a1 a2 c0 c1 c2 c3 c4
Bit
LSB 0 1 2 3 4 5 6 7 1 1 0
Bit
a0 a1 a2 c0 c1 c2 c3 c4
Function
Address Address Address RiAmp 2 RiAmp 1 CP current 1 Data-Reg Select PSC Div. Ratio
Wireless Components
5-7
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
Table 5-8 Long Control Data Formats (continued) PLL 1 Bit
8 9 10 11 12 13 14 15 16 MSB
PLL 2 Function
reserved CPP width 2 CPP width 1 standby 2 standby 1 CP polarity Mode 2 Mode 1 Sync/Async Mode
Bit
c5 c6 c7 c8 c9 c10 c11 c12 c13
Bit
8 9 10 11 12 13 14 15 16 MSB
Bit
c5 c6 c7 c8 c9 c10 c11 c12 c13
Function
MFO CPP width 2 CPP width 1 standby 2 standby 1 CP polarity IBip 2 IBip 1 Rext / Rint
Table 5-9 A/N-counter Data Formats PLL 1 Bit
LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MSB MSB LSB 0 1 0 LSB
PLL 2 Function
Address Address Address
Bit
a0 a1 a2 n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 ac0 ac1 ac2 ac3 ac4 ac5
Bit
LSB 0 1 2 3 4 5 6 7 8 1 0 1 LSB
Bit
a0 a1 a2 n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 MSB LSB n13 ac0 ac1 ac2 MSB ac3
Function
Address Address Address
N1-Counter
9 10 11 12 13 14 15 16 17 18 19
N2-Counter
A2-Counter
A1-Counter
20
Wireless Components
5-8
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
Table 5-10 R-counter Data Formats PLL 1 Bit
LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSB MSB 0 1 1 LSB
PLL 2 Function
Address Address Address
Bit
a0 a1 a2 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13
Bit
LSB 0 1 2 3 4 5 6 7 8 1 1 1 LSB
Bit
a0 a1 a2 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 MSB r13
Function
Address Address Address
R1-Counter
9 10 11 12 13 14 15 16 MSB
R2-Counter
Table 5-11 Programming of Operation and Test Modes c12 Mode 1
0 1 0 1 0 1 0 1
c11 Mode 2
0 0 1 1 0 0 1 1
c3 PLLSel
0 0 0 0 1 1 1 1
Functional Mode
TEST MODE FVN - N/A-Counter TEST MODE FRN - R-Counter NORMAL OPERATION, MFO active NORMAL OPERATION, LD of PLL1 active TEST MODE FVN - N/A-Counter TEST MODE FRN - R-Counter NORMAL OPERATION, MFO active NORMAL OPERATION, LD of PLL2 active
Affected Output:
CP1 + CP2 CP1 + CP2 LD / MFO Pin LD / MFO Pin CP1 + CP2 CP1 + CP2 LD / MFO Pin LD / MFO Pin
Table 5-12 Programming of CP Current of PLL1 c2 CP current 1
0 1 0 1
c1 Mode 2
0 0 1 1
CP Current [mA]
1.2 mA 2.0 mA 2.8 mA 4.0 mA
Remark
with 100A reference current ( Rext = 12k ohms )
Wireless Components
5-9
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
Table 5-13 Programming of CP Current of PLL2 c2 CP current 1
0 1
CP Current [mA]
Tristate 1.0 mA
Remark
with 100A reference current
Table 5-14 Programming of Charge Pump Pulse Width of both PLLs c7 CPP width 1
0 1 0 1
c6 CPP width 2
0 0 1 1
Pulse Width [ns] typ.
1.8 ns 2.7 ns 3.6 ns 4.5 ns
Remark
Table 5-15 Standby of Power Down Programming of both PLLs Control Bits c9 standby 1
0 1 0 1
Mode Pin 11 LD/fo
standby1 standby2 standby1 Operation Mode off off off active
Affected Output Pins Z: High Impedance (Tristate) Pin 3 CP1
Z Z Z active
c8 standby 2
0 0 1 1
Pin 18 CP2
Z Z Z active
Table 5-16 Programming of Synchronous/Asynchronous Mode of PLL1 c13 Sync/Async
0 1
Synchronous/Asynchronous Mode
Asynchronous Mode of PLL 1 Synchronous Mode of PLL 1
Table 5-17 Programming of PD Polarity of both PLLs Control Bit c10 PD Polarity
0 1 negative Polarity positive Polarity
PD Polarity
Wireless Components
5 - 10
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
Table 5-18 Programming of Prescaler Divide Ratio of both PLLs Control Bit c4 PSC Div. Ratio
0 1 PLL1: 32/33 PLL1: 64/65 PLL2: 8/9 PLL2: 16/17
Prescaler Divide Ratio
Table 5-19 Programming of PLL Select Control Bit c3 of PLL1
0 1 PLL1 (RF) PLL2 (IF)
PLL Select (LD mode)
Table 5-20 Programming of Data Register Select Control Bits c3 of PLL2
0 1 Data Register 1 Data Register 2
IF Data Register Select
Table 5-21 Programming of Reference Input Amplifier - RiAmp c0 of PLL2 RiAmp 2
0 1 0 1
c1 of PLL2 RiAmp 1
0 0 1 1
RiAmp Resonance Pole Position typical
9.0 MHz 11.2 MHz 19.5 MHz 28.2 MHz
Remark
VCC1=VCC2= 2V7 (2V8) nominal / recommended
Table 5-22 Programming of Bipolar Power Mode - IBip c11 of PLL2 IBip 2
0 1 0 1
c12 of PLL2 IBip 1
0 0 1 1
Bipolar Power Consumtion
nominal nominal + 20 % nominal - 40 % nominal - 20 %
RF MAX
2.8 GHz 2.8 GHz 2.0 GHz 2.5 GHz
IF MAX
0.6 GHz 0.6 GHz 0.4 GHz 0.5 GHz
Remark
nominal / recommended not recommended powersave mode II powersave mode I
Table 5-23 Programming of Rext / Rint Mode c13 of PLL2 Rext / Rint
0 1
External or Internal Reference Resistor
External @ Pin 12 - recommended Internal Polysilicone Resistor - not recommended
Wireless Components
5 - 11
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.4 Input Sensitivity
The following sections show the typical performance at +25C.
5.4.1
Typical RF Sensitivity
The PLL setup is: Psc:32/33. N:3, A:1, IF-PLL is in standby mode. VCC is 2.7 V. Chip Mode is set to 'TEST MODE FVN'. This causes the N/A divider output to be fed to the SINK part of the chargepump (source is switched off all time.) Therefore a resistor which provides a current path from pin CPx to VCP (CP supply) is needed.
SENSITIVITY - 32/33 N:3 A:1 - 2V7 - Rext - RF POW ER [dBm ] vs RF FREQUENCY [MHz] vs IBip[%]
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 0 500 100% + Rext - N ominal Mode 1000 1500 -40% + Rext - Powersave II 2000 2500 -20% + Rext - Powersave I 3000
5.4.2
Typical IF Sensitivity:
The PLL setup is: Psc:16/17. N:3, A:1, RF-PLL is in standby mode. VCC is 2.7 V..
SENSITIVITY - 16/17 N:3 A:1 - 2V5 - Rext - IF POW ER [dBm] vs IF FREQ UENCY [M Hz] vs IBip[%] 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 0 100 200 300 400 500 600 700 800 Ibip: 100% - Rext - Nominal Ibip: -40% - Rext - Powersave II Ibip: -20% - Rext - Powersave I
Wireless Components
5 - 12
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.4.3
Typical Ri Sensitivity
The PLL setup is: R:50. VCC is 2.7V. Chip Mode is set to 'TEST MODE FRN'. This causes the R divider output to be fed to the SOURCE part of the chargepump (sink is switched off all time.) Therefore a resistor which provides a current path from pin CPx to GND (CP gnd) is needed.
SENSITIVITY S1004K2#1 - R:50 - 2V7 - Rext - Ri Power [dBm] vs Ri Frequency [MHz] vs RiAmp CP->6.22kOhm->Gnd - HPcounter50ohm
5
-5
-15
-25
-35
-45
-55
-65 0 5 10 15 20 25 30 35 40
RiAmp=00b - RiRes=9.0MHz - Nominal RiAmp=10b - RiRes=19.5MHz RiAmp=01b - RiRes=11.2MHz RiAmp=11b - RiRes=28.2MHz
Wireless Components
5 - 13
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.5 Charge Pump Performance
5.5.1 Charge Pump Definition
Isnkmax Isnktyp Isnkmin
Vsrc
Vsnk
VPD/2
VCP
Isrcmin Isrctyp Isrcmax
Figure 5-1
Definition of Charge Pump Currents
Terms and Abbreviations: VPD Vsrc/snk Isnkmax Isrcmax Isnktyp Isrctyp Isnkmin Isrcmin Supply Voltage of Charge Pump Offset Voltage from GND or VPD Maximum Sink Current @ VPD-VSRC Maximum Source Current @ GND+VSNK Typical Sink Current @ VPD/2 Typical Source Current @ VPD/2 Minimum Sink Current @ GND+VSNK Minimum Source Current @ VPD-VSRC
Specification of Charge Pump Characteristics: Charge Pump Output Magnitude Variation CPMV:
Isnk - Isnk max min -------------------------------------------------2 --------------------------------------------------- 100% Isnk + Isnk max min --------------------------------------------------2 Isrc - Isrc max min ----------------------------------------------2 ------------------------------------------------ 100% Isrc + Isrc max min -----------------------------------------------2
Charge Pump Current Mismatch CPCM:
Isnk - Isrc typ typ -------------------------------------------2 --------------------------------------------- 100% Isnk + Isrc typ typ --------------------------------------------2
Wireless Components
5 - 14
Specification, May 2000
PMB 2349
preliminary
Confidential
Reference
5.5.2
Typical Performance
VCP is intended to be within VSNK and VPD-VSRC System: standard GSM-application RF: 900MHz, PD frequency: 200kHz, Vcc: 3.6V, TA.: -40...+85'C Kvco: 10MHz/V, Icp: 4mA Loopfilter (C1,R2-C2,R3,C3): 270pF,18k-2.2uF,12k,100pF The following typical performance can be expected:
Table 5-24 Typical Performance VCP-range #1 - LIBERAL VSNK = 200mV VSRC = 500mV
spurious suppression @200 kHz - better than -80 dB phase noise @ 1kHz / 2V7 - typical 85 dBc/Hz phase noise @ 1kHz / 3V6 - typical 88 dBc/Hz VSNK = 600mV VSRC = 900mV
VCP-range #2 - CONSERVATIVE
performance of VPD-range #1 CP current variation below +/-20%
5.6 Threshold Voltages of Schmitt-Trigger Input
Typical Vin Thresholds of 3W-Bus 1,32
1,22
1,12 typ. High min. typ. Low max. 1,02
0,92
0,82 2,5 3 3,5 VCC 4 4,5 5
Wireless Components
5 - 15
Specification, May 2000

▲Up To Search▲

Price & Availability of PMB2349

	To Download PMB2349 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .